Semiconductor device and fabrication process thereof

ABSTRACT

A method of fabricating a semiconductor device includes the steps of modifying a damaged layer containing carbon and formed at a semiconductor surface by exposing the damaged layer to oxygen radicals to form a modified layer, and removing the modified layer by a wet etching process, wherein the modifying step is conducted by adding an active specie of an element that would obstruct formation of double bond between a Si atom and an oxygen atom by causing a chemical bond with Si atoms on the semiconductor surface.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is based on Japanese priority application No.2004-247143 filed on Aug. 26, 2004, the entire contents of which arehereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention generally relates to fabrication of semiconductordevices and more particularly to a fabrication method of a semiconductordevice having a very shallow junction.

With recent highly miniaturized, ultra-fast semiconductor devices,having a gate length of typically 90 nm or less, such as the one havingthe gate length of 50 nm or 40 nm, the diffusion regions constitutingthe source and drain regions of the transistor have a very shallow depthof about 20 nm or less.

When fabricating such a semiconductor device having a very shallowjunction, particular caution has to be taken in the dry etching processthat exposes the diffusion region.

With regard to the dry etching process used in the fabrication processof a MOS transistor, there can be two situations in which the dryetching process causes exposure of the diffusion regions, the firstbeing the one used for forming a contact hole in an insulation film, andthe other being the one used for forming sidewall insulation films onthe sidewall surfaces of the gate electrode. In any of these processes,it is generally practiced to carry out the etching process of theinsulation film by using a fluorocarbon (CF) family gas orhydrofluorocarbon (CHF) family gas for the etching gas.

At the time of the dry etching of an insulation film with an etching gasof the CF or CHF family gas, plasma is used for causing dissociation inthe etching gas to form radicals or ions of active species such as F(fluorine) contained in the etching gas, and the ions of the activespecies thus formed are caused to react upon the substrate to beprocessed by accelerating the same by using a substrate bias electricfield. Further, at the time of such an etching process, it is generallypracticed to carry out so-called overetching, in view of possiblevariation of the film thickness or variation of the etching rate, inwhich the etching is continued for a predetermined duration after thesilicon substrate surface is exposed, such that the silicon surfaceconstituting the diffusion region is exposed completely.

On the other hand, with such an overetching process, it is generallyunavoidable that the silicon surface is etched more or less as a resultof the action of the etching gas to the exposed silicon surface.Particularly, the silicon surface is tend to be etched by F.

In view of the situation noted above, there is an increasing tendency touse gases of high C (carbon) proportion such as C₄F₈ or C₄F₆, for the CFor CHF family etching gas, for suppressing the etching of the siliconsurface and thus increasing the etching selectivity at the time of theoveretching process. By using such an etching gas of high C proportion,there is caused deposition of C on the silicon surface exposed by theetching, and the undesirable etching of the silicon surface at the timeof the overetching is suppressed.

(Patent Reference 1) Japanese Laid-Open Patent Application 8-78352(Patent Reference 2) Japanese Laid-Open Patent Application 9-129602

(Non-Patent Reference 1) K. Hashimi et al., Jpn. J. Appl. Phys. vol. 35,(1996), pp. 2494

SUMMARY OF THE INVENTION

In an aspect of the present invention, there is provided a method offabricating a semiconductor device, comprising the steps of:

modifying a damaged layer containing carbon and formed at asemiconductor surface by exposing said damaged layer to oxygen radicalsto form a modified layer; and

removing said modified layer by a wet etching process,

said modifying step being conducted by adding to said damaged layer anactive specie of an element that would obstruct formation of double bondbetween a Si atom and an oxygen atom by causing a chemical bond with Siatoms on said semiconductor surface.

In another aspect of the present invention, there is provided asemiconductor device, comprising:

a semiconductor substrate;

a gate electrode formed on a principal surface of said semiconductordevice via a gate insulation film;

source and drain regions formed on said semiconductor substrate atrespective lateral sides of said gate electrode; and

stepped parts formed at respective lateral sides of sidewall insulationfilms formed at respective sidewall surfaces of said gate electrode,said stepped parts having a step height of 5 nm or less.

According to the present invention, it becomes possible to facilitateconversion of the damaged layer to the modified layer removable by wetetching, as compared with the case of using oxygen radicals alone, byadding, with a suitable amount, an element that would obstruct formationof double bond between a Si atom and an oxygen atom by causingpreferential bonding with Si atoms on the semiconductor surface.Thereby, by conducting the modifying step such that there is caused noetching in the damaged layer, it becomes possible to avoid formation ofthe stepped part to have a step height beyond the initial thickness ofthe damaged layer, and it becomes possible to avoid formation of stepsat the semiconductor surface with such a step height that would causeinfluence upon the operational characteristics of the semiconductordevice. The present invention is particularly useful in the fabricationof ultrahigh-speed semiconductor devices fabricated by using very smallion injection energy at the time of ion implantation process of impurityelements, which is comparable with the energy of the etching gas speciesacting upon the substrate at the time of dry etching process.

Other objects and further features of the present invention will becomeapparent from the following detailed description when read inconjunction with the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1D are diagrams showing the formation process of a contact plugaccording to the related art of the present invention;

FIG. 2 is a diagram explaining the problems associated with the relatedart of FIG. 1;

FIGS. 3A-3D are diagrams for fabricating a semiconductor deviceaccording to another related art of the present invention;

FIGS. 4A-4C are diagrams explaining further related art of the presentinvention;

FIGS. 5A-5C are diagrams explaining the problems associated with therelated art of FIGS. 4A-4D;

FIG. 6 is another diagram explaining the problems associated with therelated art of FIGS. 4A-4D;

FIG. 7 is a diagram showing the construction of a plasma processingapparatus used with the present invention;

FIGS. 8A-8C are diagrams showing a substrate processing method accordingto a first embodiment of the present invention;

FIG. 9 is a diagram showing the evaluation of the substrate processingmethod of FIGS. 8A-8C;

FIGS. 10A-10J are diagrams showing the fabrication process of asemiconductor device according to a second embodiment of the presentinvention;

FIG. 11 is a diagram showing a modification of the second embodiment ofthe present invention;

FIG. 12 is a diagram showing the characteristics of the semiconductordevice according to a second embodiment of the present invention;

FIG. 13 is another diagram showing the characteristics of thesemiconductor device of the second embodiment;

FIGS. 14A-14F are diagrams showing the fabrication process of asemiconductor device according to a third embodiment of the presentinvention;

DETAILED DESCRIPTION OF THE INVENTION

On the other hand, in the case such a CF or CHF family etching gascontaining C with large proportion is used, there arises a problem inthat C deposited on the silicon surface and preventing the etching ofthe exposed silicon surface is not simply deposited on the exposedsilicon surface but is in fact impinged thereto as a result of thefunction of the electric field caused by the substrate biasing, andthus, there is formed a damaged layer (deteriorated layer) at theexposed surface of the silicon substrate, wherein it should be notedthat the damaged layer contains SiC formed by the impinged C atomscausing a chemical bond with a Si atom on the silicon surface. Such anSiC layer has a large resistivity and causes increase of contactresistance in the metal plug formed in contact with the exposed siliconsurface. Such increase of the contact resistance thus causes unwanteddecrease of operational speed of the semiconductor device.

FIGS. 1A-1D show an example of formation of the damaged layer in such acontact hole.

Referring to FIG. 1A, there is formed a diffusion region 11 a of p-typeor n-type in a silicon substrate 11, and an insulation film 12 of SiO₂,or the like, is formed on the surface of the silicon substrate 11.

In the step of FIG. 1A, there is formed a resist pattern 13 having anopening 13A on the insulation film 12, and the insulation film 12 isremoved by a dry etching process that uses an etching gas of the CHFfamily, while using the resist pattern 13 as a mask. As a result, thereis formed a contact hole 12A in the insulation film 12 in correspondenceto the resist opening 13A.

FIG. 1B shows the state in which the surface of the silicon substrate 11is just exposed as a result of the foregoing dry etching process,wherein it will be noted that there remains a residue 12 x of theinsulation film 12 formed as a result of non-uniformity of the etching.

Thus, in the step of FIG. 1C, the overetching is conducted by continuingthe dry etching process. With this, the residual insulation film 12 x isremoved completely, while such an overetching process also causesimplantation of C contained in the etching gas into the siliconsubstrate 11. Thus, there is formed a damaged layer 11 b containing C atthe surface of the silicon substrate 11 in correspondence to the bottompart of the contact hole 12A. In such a damaged layer 11 b containing C,it is believed that the C atoms thus implanted form SiC by causing achemical bond with the Si atoms in the silicon substrate 11. It shouldbe noted that formation of such a damaged layer becomes particularlyconspicuous in the step of contact-hole formation of FIG. 1B when theetching gas of high C concentration such as C₄F₈ or C₄F₆ for securingetching selectivity against the silicon substrate is used.

Further, in the step of FIG. 1D, the contact hole 12A is filled with ametal such as W. Further, by removing excess metal film by a chemicalmechanical polishing process or the like, there is formed a contact plug14 in contact with the diffusion region 11 a via the SiC layer 11 b. Inthe example of FIG. 1D, it will be noted that there is formed anadhesion/diffusion barrier layer 14A of Ta/TaN structure between thecontact plug 14 and the silicon substrate 11 or the insulation film 12.

FIG. 2 shows the change of sheet resistance of the diffusion region 11 aassociated with the formation of the damaged layer 11 b containing SiC.

In FIG. 2, it should be noted that the vertical axis represents thesheet resistance of the diffusion region 11 a formed with the damagedlayer 11 b, while the horizontal axis represents the thickness of thedamaged layer 11 b.

Referring to FIG. 2, the sheet resistance, and hence the contactresistance, takes the value of about 0.6 kΩ/sq in the case there existsno such a damaged layer 11 b, while in the case the damaged layer 11 bis formed with the thickness of 4 nm, it can be seen that the sheetresistance increases to about 3.6 k Ω/sq.

It should be noted that formation of similar SiC layer is caused also inthe case of forming the sidewall insulation films at both sidewallsurfaces of the gate electrode.

FIGS. 3A-3D show the fabrication process of a semiconductor deviceincluding the formation process of such sidewall insulation films.

Referring to FIG. 3A, there is formed a polysilicon gate electrode 23 ona silicon substrate 21 of p-type or n-type via a gate insulation film22, wherein there is provided an insulation film 24 of Si₃N₄, SiO₂ orSiON on the silicon substrate 21 by a CVD process, or the like, so as tocover the gate electrode 23 in conformity with the shape of the gateelectrode 23.

Next, in the step of FIG. 3B, an anisotropic etching process actinggenerally perpendicularly to the silicon substrate 21 is applied to theinsulation film 24 of FIG. 3A by using an etching gas of CF family orCHF family, such that the insulation film 24 is removed from the surfaceof the gate electrode 23 and from the surface of the silicon substrate21. Here, it should be noted that FIG. 3B shows the state just theinsulation film 24 has been removed from these surfaces, wherein it willbe noted that there remain residues 24 x of the insulation film 24 onthe surface of the gate electrode 23 or on the surface of the siliconsubstrate 21 due to the non-uniformity of etching. Again, it should benoted that a gas of high C concentration such as C₄F₈ or C₄F₆ is used asthe foregoing CF family gas or CHF family gas for securing sufficientetching selectivity between the insulation film 24 and the siliconsubstrate 21.

Further, in order to remove the foregoing residues 24 x of FIG. 3B, anoveretching is conducted in the step of FIG. 3C by continuing the dryetching process of FIG. 3B. With this overetching, on the other hand,there occurs implantation of C in the etching gas into the polysilicongate electrode 23 and the silicon substrate 21, and as a result, thereis formed a damaged layer 25 containing SiC, in which C is bonded withSi, at the surface of the polysilicon gate electrode 23 and at theexposed surface of the silicon substrate 21.

It should be noted that the damaged layer 25 thus formed not only causesincrease of diffusion regions resistance and contact resistance asexplained with reference to FIG. 3, but also capturing or blockade ofimpurity element introduced in the ion implantation process of FIG. 3D.Thereby, the impurity concentration is reduced inevitably in the gateelectrode 23 or in the diffusion regions formed at both lateral sides ofthe gate electrode 23.

More specifically, in the step of FIG. 3D, the impurity element ofn-type or p-type is introduced to the structure of FIG. 3C and thepolysilicon gate electrode 23 is doped to the n-type or p-type as aresult. At the same time, as a result of the ion implantation process ofFIG. 3D, diffusion regions 21 a and 21 b of the same conductivity typeare formed in the silicon substrate 21 at respective outer sides of thepolysilicon gate electrode 23.

Here, it should be noted that, because of existence of the damaged layer25 formed at the surface part of these regions, the impurity elementthus injected are captured at least partly by the damaged layer 25.Thereby, the impurity element does not reach the gate electrode 23 orthe diffusion regions 21 a and 21 b with sufficient amount, and thus,there can be caused problems in that the impurity concentration does notreach the predetermined concentration level in the gate electrode 23 andin the diffusion regions 21 a and 21 b.

In order to deal with this problem, Japanese Laid-Open PatentPublication 8-78352 proposes the technology of applying an O₂ RIEprocess to the damaged layer 25 and converts the same to an SiO₂ layer.The damaged layer thus converted to the SiO₂ layer is then removed by awet etching process or the like in an HF etchant.

FIGS. 4A-4C show the processing according to the foregoing conventionalproposal, wherein those parts corresponding to the parts describedpreviously are designated by the same reference numerals and thedescription thereof will be omitted.

Referring to FIG. 4A, this state corresponds to the state of FIG. 3C,and thus, the damaged layer 25 is formed on the surface of the siliconsubstrate 21 and on the surface of the polysilicon gate electrode 23.

Thus, in the step of FIG. 4B, oxygen ions are injected into thestructure of FIG. 4A by conducting an O₂ RIE processing, and the damagedlayer 25 is converted to an SiO₂ layer 25A.

Further, by removing the SiO₂ layer 25A thus formed by a wet etchingprocess in the step of FIG. 4C, the part corresponding to the damagedlayer 25 is removed. Thereby, the substrate 21 is removed at the partlocated outside the sidewall insulation films 24A and 24B, and as aresult, there is formed a stepped part 21G in correspondence to the partthus removed by the wet etching process.

However, with such an O₂ RIE processing conducted under substratebiasing, it is difficult to control the injection depth of the oxygenions, and the oxygen ions penetrate deeply into the silicon substrate 21or into the polysilicon gate electrode 23 beyond the desired depth asindicated in FIGS. 5A-5C by arrows. Thereby, there is a substantial riskthat the depth of the stepped part 21G formed in the silicon substrate21 after the wet etching process is increased. Here, it should be notedthat FIGS. 5A-5C correspond to FIGS. 4A-4C, respectively.

Thus, in the case a semiconductor device is formed by conducing ionimplantation of impurity element into the structure having such astepped part 21G, there appears a parasitic resistance R at such astepped part 21G as represented in FIG. 6. Thereby, the operationalspeed of the semiconductor device is deteriorated. In FIG. 6, thoseparts corresponding to the parts explained previously are designated bythe same reference numerals and the description thereof will be omitted.It should be noted that such a problem appears particularlyconspicuously in the ultrahigh-speed semiconductor devices having a gatelength of 90 nm or less.

Further, in such ultrahigh-speed semiconductor devices, it is generallypracticed to form a pocket injection region 21 p prior to the formationof the sidewall insulation films 24A and 24B as shown in FIG. 6 forsuppressing short-channel effect by injecting an impurity element of thesame conductivity type as the channel impurity element obliquely rightunderneath the gate electrode, while the effect of the pocket injectionregion 21 p of suppressing the short channel effect is vanished when theamount of etching in the step of FIG. 5C is larger than the thickness ofthe pocket injection region 21 p and the stepped part 21G goes throughthe pocket region 21 p.

FIRST EMBODIMENT

FIG. 7 shows the construction of a down-flow plasma processing apparatus40 used with the present invention.

Referring to FIG. 7, the down-flow plasma processing apparatus 40includes a processing vessel 41 evacuated at an evacuation port 41B anddefining a processing spate 41A, wherein a stage 41C is provided in theprocessing vessel 41 for supporting a substrate W to be processed.

In the processing vessel 41, there is further provided a showerhead 43so as to face the substrate W to be processed, wherein gas lines 44A,44B, 44C, 44D and 44E are connected to the showerhead 43 respectivelyfor supplying a rare gas such as Ar, a fluorocarbon gas such as CF₄, anoxygen gas, a hydrogen gas and a nitrogen gas. Further, a microwavepower is supplied to the showerhead 43 from a microwave source 45, andan RF power is supplied to the stage 41C from an RF source 46. Theshowerhead 43 is formed of a stainless steel and holds therein ashowerhead body 43A of a quartz glass.

In the investigation constituting the foundation of the presentinvention, the inventor of the present invention has conductedexperiments of modifying a damaged layer containing SiC and formed on asilicon substrate by using the apparatus 40 of FIG. 7 and furtherremoving the same by a wet etching process.

FIGS. 8A-8C explain the foregoing experiments.

Referring to FIG. 8A, a silicon substrate 60 is introduced into theprocessing vessel 41 of the plasma processing apparatus 40 of FIG. 7 andis placed on the stage 41C as a wafer W.

Next, the processing vessel 41 is evacuated such that the processingpressure in the processing space 41A is set to about 10 Pa.

Further, an Ar gas is introduced into the processing space 41A from thegas line 44A with a flow rate of 500 SCCM, and microwave plasma isformed in the processing space 41A by supplying a microwave power of2.45 GHz to the showerhead 43 from the microwave source 45 with a powerof 1000 W.

Further, an RF power of 200 kHz-100 MHz is supplied to the stage 41Cfrom the RF source 46, and as a result, a D.C. bias is formed in thesubstrate W to be processed.

In this state, a CF gas or CHF gas having a high carbon concentrationsuch as C₄F₈ is introduced into the processing space 41A from the gasline 44B, and a process corresponding to the overetching process of FIG.1C is applied to the surface of the silicon substrate 60. With this, adamaged layer 61 containing SiC is formed on the surface of the siliconsubstrate 60 with the thickness of 5 nm.

Next, in the step of FIG. 8B, the RF source 46 is deenergized and theprocessing space 41A is purged with an Ar gas from the line 44A.Further, while maintaining the processing space 41A to the processingpressure of 500 Pa, a modifying step of the damaged layer 61 isconducted by supplying the Ar gas from the gas line 44A, the CF₄ gasfrom the gas line 44B, the oxygen gas from the gas line 44C, thehydrogen gas from the gas line 44D and the nitrogen gas from the gasline 44E into the processing space 41A.

In the step of FIG. 8B, it should be noted that no substrate bias isapplied to the substrate W to be processed. Thus, there occurs noacceleration of ions in the plasma by the biasing electric field appliedto the substrate W to be processed, and thus, there occurs no collisionof accelerated ions with the substrate W in the step of FIG. 8B.

Thereby, the damaged layer 61 at the surface of the substrate 60 isexposed to the oxygen radicals O* formed from the oxygen gas, hydrogenradicals H* formed from the hydrogen gas, fluorine radicals F* formedfrom the CF₄ gas and the nitrogen radicals N* formed from the nitrogengas, and as a result, the damaged layer 61 undergoes a chemicalmodification process, causing a conversion of the same partly or totallyto a modified layer 61A primarily formed of SiO₂.

Further, in the step of FIG. 8C, the silicon substrate 60 having themodified layer 61A is subjected to a wet etching process of HF, and themodified layer 61A is removed selectively with regard to the siliconsubstrate 60. In the example of FIG. BC, it can be seen that thereremains a damaged layer 61 not modified on the silicon substrate 60.

FIG. 9 shows the thickness of the modified layer 61A for variouscombinations of the gases supplied in the step of FIG. 8B, together withthe thickness of the modification layer 61A for the state in which thewet etching step of FIG. 8C is conducted. In FIG. 9, the vertical axisrepresents the thickness of the modified layer 61A on the siliconsubstrate 60, while the horizontal axis represents the combination ofthe gases. In FIG. 9, the black graph represents the thickness of themodified layer 61A in the state of FIG. 8B, while the white graphrepresents the thickness of the modified layer 61A in the state of FIG.8C. Further, the grey graph represents the thickness of the modifiedlayer 61A in the case the duration of the wet etching process isincreased further in the step of FIG. BC.

In FIG. 9, it should be noted that the experiment (I) represents theresult in which the modifying step of FIG. 8B is conducted by solelysupplying the oxygen gas of the gas line 44C with the flow rate of 1000SCCM, while the experiment (II) represents the result in which themodifying step of FIG. 8B is conducted by supplying, in addition to theoxygen gas from the gas line 44C with the flow rate of 1000 SCCM, theCF₄ gas in the gas line 44B with the flow rate of 10 SCCM, the hydrogengas in the gas line 44D with the flow rate of 10 SCCM, and the nitrogengas in the gas line 44E with the flow rate of 500 SCCM. Further, theexperiment (III) represents the result for the case in which themodifying step of FIG. 8B is conducted by supplying, in addition to theoxygen gas from the gas line 44C with the flow rate of 1000 SCCM, theCF₄ gas in the gas line 44B with a larger flow rate of 50 SCCM, thehydrogen gas in the gas line 44D with the flow rate of 10 SCCM and thenitrogen gas in the gas line 44E with the flow rate of 500 SCCM, whilethe experiment (IV) represents the result for the case in which themodifying step of FIG. 8B is conducted by supplying, in addition to theoxygen gas from the gas line 44C with the flow rate of 1000 SCCM, thehydrogen gas in the gas line 44D with the flow rate of 10 SCCM, thenitrogen gas in the gas line 44E with the flow rate of 500 SCCM.Contrary to this the experiment (V) of FIG. 9 represents the result inwhich the modifying step of FIG. 8B is conducted by supplying, inaddition to the oxygen gas from the gas line 44C with the flow rate of1000 SCCM, the CF₄ gas in the gas line 44B with the flow rate of 10 SCCMsuch that the ratio of the oxygen gas and the CF₄ gas becomes 100:1.

In all the experiments, it should be noted that the foregoing modifyingstep is conducted under the processing pressure of 500 Pa whilesupplying the microwave power of 1000 W to the showerhead 43. Further,as noted before, no substrate bias is applied in the modifying step ofFIG. 8B.

Referring to FIG. 9, it can be seen that the thickness of the damagedlayer 61 has not changed from the initial thickness of 5 nm in theexperiments (I)-(IV) even when the modifying step of FIG. 8B isconducted, indicating that there has been caused no thickness loss inthe modifying step of FIG. 8B. Contrary to this, in the experiment (V),it can be seen that the initial thickness of 5 nm has been decreased toabout 2 nm as a result of the modifying step, indicating that there hasbeen caused a loss of Si at the silicon surface as a result of themodifying step and that there can occur encroachment of the siliconsurface when the processing condition of the modifying step isinappropriate.

In the experiment (I), on the other hand, it can be seen that themodified layer 61A remains after the wet etching process of FIG. 8C isconducted after the modifying step of FIG. 8B with the thickness ofabout 3 nm, while this indicates that the modifying reaction has notproceeded sufficiently and the damaged layer 61 of FIG. 8A has been leftwith the thickness of about 3 nm.

In the experiment (II), on the other hand, it will be noted that thethickness of the modified layer 61A remaining on the silicon substrate60 after the wet etching process has been decreased further by addingthe nitrogen gas and the hydrogen gas and the CF4 gas to the oxygen gas,indicating that the modifying reaction has proceeded more effectively.Further, as can be seen in experiment (III), the efficiency of themodifying reaction is improved by increasing the proportion of the CF₄gas. In the experiment (II), it should be noted that the oxygen gas,nitrogen gas, hydrogen gas and the CF₄ gas are used with the ratio of100:50:1:1 (100:1 ratio for the oxygen gas an the CF₄ gas), while in theexperiment (III), the oxygen gas, the nitrogen gas, the hydrogen gas andthe CF₄ gas are used with the ratio of 100:50:1:5 (20:1 ratio for theoxygen gas and the CF₄ gas).

Further, as shown in the experiment (IV), it will be noted that theefficiency of the modifying reaction is improved as compared with thecase of the experiment (I) by merely adding the nitrogen gas and thehydrogen gas to the oxygen gas.

When such a further gas such as the hydrogen gas or the CF family gas isadded to the oxygen radicals, there are formed hydrogen radicals or Fradicals in the processing space 41A as a result of the plasmaexcitation of these added gases, while it is believed that theseradicals replace the C atoms in the damaged layer 61 of FIG. 8A promptlyand the damaged layer 61 is converted to the HF-soluble film of SiOH orSiOF. Thus, by adding the hydrogen radicals or F radicals having highreactivity with Si and thus obstructing formation of double bond betweenthe Si atoms and the oxygen atoms to the oxygen radicals with a suitableamount in the modifying step of FIG. 8B, formation of stable SiO₂ filmat the surface of the damaged layer 61 preventing further modificationof the interior of the damaged layer 61 is suppressed, and themodification region of FIG. 8B penetrates deeply into the damaged layer61.

Particularly, as can be seen in the experiment (III), the modifyingreaction proceeds deeply into the interior of the film by increasing theproportion of the F radicals, and it is thought preferable to increasethe amount of the CF gas added in the step of FIG. 8B. On the otherhand, it is also indicated from the experiment (V) that excessive Fradicals can cause etching of the silicon substrate in the modifyingstep of FIG. 8B. In this case, there can be caused unwanted formation ofstepped part explained previously.

SECOND EMBODIMENT

FIGS. 10A-10J are diagrams showing the fabrication process of asemiconductor device 80 according to a second embodiment of the presentinvention for the case of fabricating a p-channel MOS transistor.

Referring to FIG. 10A, the semiconductor device 80 is formed on ann-type device region 81 defined on a silicon substrate 81 by an STIdevice isolation structure 81B, wherein, in the state of FIG. 10A, thereis formed a polysilicon gate electrode 83 having a gate length of 90 nmor less such as the one having the gate length of 40 nm on the deviceregion 81A via an SiON gate insulation film 82 having the thickness of 1nm.

Next, in the step of FIG. 10B, P+ (or As+ or Sb+) is introduced into thesilicon substrate with an oblique ion implantation process conductedunder the acceleration voltage of 30 keV with a dose of 1×10¹³ cm⁻²while using the polysilicon gate electrode 83 as a mask, and as aresult, there are formed n-type pocket injection regions 81 p at bothlateral sides of the gate electrode 83, such that the respective tip endparts of the pocket injection regions 81 p invade under the channelregion right underneath the gate electrode 83.

Further, in the step of FIG. 10B, B+ is introduced under theacceleration voltage of 1 keV with the dose of about 1×10¹⁵ cm⁻² whileusing the polysilicon gate electrode 83 as a mask, and there are formeda source extension region 81 a and a drain extension region 81 b ofp-type at both lateral sides of the gate electrode 83.

Further, in the step of FIG. 10C, a silicon oxide film 84 is depositedon the structure of FIG. 10B by a CVD process so as to cover the surfaceof the silicon substrate 81 and the gate electrode 83, and the siliconoxide film 84 thus deposited is etched back in the step of FIG. 10D by adry etching process that uses a CF family gas or CHF family gas such asC₄F₈. With this, sidewall insulation films 84A and 84B are formed on therespective sidewall surfaces of the polysilicon gate electrode 83. Thisetch back process of FIG. 10C may be conducted by using the plasmaprocessing apparatus such as the down-flow plasma processing apparatusof FIG. 7 while applying a substrate bias to the substrate W to beprocessed.

As a result of such a plasma etching process, there are exposed thesurface of the silicon substrate 81 at the respective outer sides of thesidewall insulation films 84A and 84B and also the surface of thepolysilicon gate electrode 83. Thereby, carbon in the etching gas isinjected to the exposed silicon surface as a result of the substratebias electric field, and there is formed a damaged layer 85 containingSiC on such a surface with the thickness of several nanometers.

Thus, in the present embodiment, there is conducted a modifying processthat modifies the damaged layer 85 primarily formed of SiC to a modifiedlayer 85A formed primarily of SiO₂ soluble to HF and containing furtherSiOF or SiOH by using the down-flow plasma processing apparatus 40 ofFIG. 7 and by supplying a nitrogen gas, a hydrogen gas and a CF or CHFgas to the processing space 41A in addition to the oxygen gas, withoutapplying the substrate bias. It should be noted that this modifyingprocess can be conducted by the condition similar to the one used withthe experiments (II)-(IV) in the modifying process of FIG. 8B explainedpreviously.

Next, in the step of FIG. 10F, the structure of FIG. 10E is subjected toa wet etching process in HF and the modified layer 85A is removed.

In the step of FIG. 10F, there is formed a stepped part 81G on thesurface of the silicon substrate 81 with the wet etching of themodifying layer 85A, while in the present embodiment, the modified layer85 is not etched during the modifying step of FIG. 10E, and thus, theheight of the stepped part 81G never exceeds the initial thickness ofthe damaged layer 85. In the example of FIG. 10F, it will be noted thatthere remains a small amount of unreacted damaged layer 85 after the wetetching process by HF as the residual modified layer 85A.

Thereby, it should be noted that the thickness of the residual modifiedlayer 85A can be minimized or made zero by optimizing the modifyingprocess of FIG. 10E. Thus, it becomes possible to make the thickness ofthe residual modified layer 85A after the wet etching process of FIG.10F to almost zero without etching the modified layer 85. In this case,there occurs no etching of the silicon surface underneath the residualmodified layer 85A.

Next, in the step of FIG. 10G, there is conducted an ion implantationprocess of B+ into the silicon substrate 81 under the accelerationelectrode of 0.5 keV or less with a high dose of 5.0×10¹⁵ cm⁻² whileusing the gate electrode 85 and the sidewall insulation films 84A and84B as a mask. Thereby, source and drain diffusion regions 81 c and 81 dare formed at respective outer sides of the sidewall insulation films84A and 84B such that the source diffusion region 81 c partiallyoverlaps with the source extension region 81 and the drain diffusionregion 81 d partially overlaps the drain extension region 81 b. At thesame time, the polysilicon gate electrode 83 is doped by B+ to a highconcentration level.

In the step of FIG. 10G, in which the damaged layer 85, formed at theexposed part of the silicon substrate 81 and thus at the sourcediffusion region 81 c and the drain diffusion region 81 d and further atthe exposed part of the gate electrode 83, is removed or partiallyremoved as a result of the wet etching process of FIG. 10F after themodifying step of FIG. 10E, the ion implantation process of FIG. 10G isconducted efficiently and effectively without the problem of theinjected impurity element being captured by the modified layer 85. Thus,with the present invention, the source and drain diffusion regions 81 cand 81 d are doped with high concentration and the source resistance ofthe semiconductor device is reduced successfully. Further, the gateelectrode 83 is doped to a high concentration level, and the problem ofgate depletion, which tends to occur with such ultrahigh-speedsemiconductor devices, can be suppressed effectively.

Further, in the step of FIG. 10H, there is formed a silicide layer 86 ofcobalt silicide or nickel silicide at the surface of the diffusionregions 81 c and 81 d and further at the surface of the polysilicon gateelectrode 83 by a salicide process, and an interlayer insulation film 87is deposited on the structure of FIG. 10H in the step of FIG. 10I.Thereby, there are formed contact holes 87A and 87B in the interlayerinsulation film 87 respectively in correspondence to the diffusionregions 81 c and 81 d in the step of FIG. 10I so as to expose therespective silicide layers 86.

Finally, in the step of FIG. 10J, the contact holes 87A and 87B arefilled with conductive plugs 88A and 88B.

It should be noted that the MOS transistor thus fabricated hasadvantageous features, in addition to the feature that the source anddrain diffusion regions 81 a and 81 b and the polysilicon gate electrode83 are doped to high concentration level, in that the stepped partformed as a result of the wet etching process of FIG. 10F has a smallstep height. Thus, there occurs no problem such as the bottom of thestepped part 81G comes close to the bottom edge of the pocket injectionregion 81 p or the bottom edge of the source and drain extension regions81 a and 81 b, or goes through the same. Thereby, the problems such asvariation of threshold characteristics with decrease of the gate lengthor increase of the leakage current are suppressed. Further, in thesilicide formation step of FIG. 10H, too, the thickness of the damagedlayer 85 formed at the surface on which the silicide layer 86 is formed,is decreased, and thus, the defects in the silicide layer 86 is reduced.

Further, while not illustrated, a similar process can be used also forfabricating an n-channel MOS transistor.

Ideally, the damaged layer 85 is converted to the modified layer 85A forthe entire thickness in the step of FIG. 10E and is removed entirelywith the step of FIG. 10F, as represented in FIG. 11. It should be notedthat FIG. 11 corresponds to FIG. 10F and further explanation thereofwill be omitted.

While the foregoing explanation was made for the case of using thedown-flow plasma processing apparatus 40 of FIG. 7 for the plasmaprocessing apparatus in the modifying process of FIG. 10E, the presentinvention is by no means limited to such a specific plasma processingapparatus of specific type, and it is also possible to use other plasmaprocessing apparatuses including the apparatus of parallel plate type,ECR type, ICP type, toroidal type, and the like.

FIG. 12 shows the relationship between the threshold value Vth and thegate length Lg of a p-channel MOS transistor for the case in which thestepped part 81G formed in the wet etching process of FIG. 10F has cometo the depth of about 3 nm under the damaged layer 85 (represented byopen circles) and the case in which the stepped part 81G has reached thedepth of about 4 nm under the damaged layer 85 (represented by solidcircles).

Referring to FIG. 12, it can be seen that the variation of the thresholdvalue is very small in the case the stepped part 81G at the siliconsubstrate surface is about 3 nm as long as the gate length is within therange of 50-90 nm. On the other hand, in the case the stepped part 81Gat the silicon substrate surface is about 4 nm, it can be seen that thevariation of the threshold value increases sharply when the gate lengthLg has become smaller than about 70 nm. This indicates that, with suchincrease of depth of the stepped part 81G, the surface of the siliconsubstrate 81 comes close to the bottom edge of the pocket injectionregion 81 p and the function of the pocket injection region 81 p ofsuppressing the short channel effect is no longer working effectively.

FIG. 13 shows the relationship between the on-current Ion and the gatelength Lg for the MOS transistor obtained with the present invention,wherein FIG. 13 shows the results for an n-channel MOS transistor. InFIG. 13, the open circles represent the result for the specimen in whichthe stepped part 81G has reached the depth of about 3 nm underneath thedamaged layer 85, while the solid circles represent the result for thecase in which the stepped part 81G has reached the depth of about 4 nmunder the damaged layer 85.

Referring to FIG. 13, in the case the encroachment (Si loss) underneaththe damaged layer 85 is small, it can be seen that the decrease of theon-current with decrease of the gate length is relatively small, whilein the case there is a large Si loss, there occurs a remarkable decreasein the on-current. In any of these cases, there can be seen no change ofsheet resistance. Thus, it is believed that the result of FIG. 13reflects the increase of parasitic resistance caused with increase inthe step height of the stepped part 81G.

Contrary to this, with the present embodiment, the etching does notproceed beyond the bottom edge of the damaged layer 85 in the wetetching process of FIG. 10F, and thus, there is caused no excessive Siloss. Thereby, the short channel effect is suppressed minimum, and itbecomes possible to secure stable threshold characteristics andsufficient on-current value even in the case the gate length is reducedto 40 nm or less.

THIRD EMBODIMENT

FIGS. 14A-14D are diagrams showing the process of forming a contact holeaccording to a third embodiment of the present invention.

Referring to FIG. 14A, there is formed a diffusion region 101 a ofp-type or n-type in a silicon substrate 101, and an insulation film 102of SiO₂ or the like is formed on the surface of the silicon substrate101. Particularly, it should be noted that the diffusion region 101 a ofFIG. 14A is formed, in view of possible application thereof toultrahigh-speed semiconductor devices having the gate length of 90 nm orless, such that bottom edge of the diffusion region is located at adepth of 20 nm or less as measured from the substrate surface.

In the step of FIG. 14A, there is formed a resist pattern 103 having anopening 103A on the insulation film 102, and the insulation film 102 isremoved by a dry etching process that uses an etching gas of CF or CHFfamily while using the resist pattern 103 as a mask. With this, there isformed a contact hole 102A in the insulation film 102 in correspondenceto the resist opening 103A.

FIG. 14B shows the state just after the surface of the silicon substrate101 is exposed as a result of the foregoing dry etching process. In thiscase, it will be noted that there remains a residue 102 x of theinsulation film 102 at the bottom of the contact hole 102A as a resultof non-uniformity of the etching process.

Thus, in the step of FIG. 14C, the dry etching process is continued andthe overetching is conducted. With this, the residue 102 x of theinsulation film 102 is removed completely, while such a process alsocauses formation of a damaged layer 101 b containing SiC at the surfaceof the silicon substrate in correspondence to the bottom part of thecontact hole 102A as a result of injection of C in the etching gas intothe silicon substrate 101.

Thus, with present embodiment, a modifying processing is applied to thedamaged layer 101 b in the step of FIG. 14D by using the oxygenradicals, hydrogen radicals and the fluorine radicals under thecondition such that there is caused no etching in the damaged layer 101b, and with this, at least a part of the damaged layer 101 b isconverted to a modified layer 101 c formed primarily of SiO₂ and furthercontaining SiOF or SiOH.

Further, in the step of FIG. 14E, the structure of FIG. 14D is treatedwith a wet etching process in a diluted hydrofluoric acid solution.Thereby the modified layer 101 c is removed.

Further, in the step of FIG. 14F, the inner wall surface of the contacthole 12A is covered by an adhesion/diffusion barrier layer 104 ofTa/TaN, or the like, and a contact plug 104 is formed by filling thecontact hole 12A with a metal such as W.

In the present embodiment, too, the encroachment at the bottom part ofthe contact hole 12A becomes minimum at the time of the step of removingthe modified layer, and thus, it becomes possible to form a contact oflow contact resistance while minimizing the effect caused in the shallowdiffusion region 101 a. With this, it becomes possible to minimize thewiring resistance in ultrafine high-speed semiconductor devices.

Further, while the present invention has been explained heretofore forthe example of formation of sidewall insulation films and fine contactholes in ultra-fast semiconductor devices having a gate length of 90 nmor less, it should be noted that the present invention is applicablealso to fabrication of various semiconductor devices including DRAMshaving-fine contact holes.

Further, in the modifying process of the present invention, it ispossible to use other F-containing gases such as an SF₆ gas, in additionto the fluorocarbon gas as the source of the fluorine radicals.

Further, the present invention is not limited to the embodimentsdescribed heretofore, but various variations and modifications may bemade without departing from the scope of the invention.

1. A method of fabricating a semiconductor device, comprising the stepsof: forming a gate electrode over a surface of a semiconductorsubstrate; depositing a film so as to cover said gate electrode and saidsurface of said semiconductor substrate; etching said film to formsidewall insulation films at both sidewalls of said gate electrode byusing a gas containing fluorocarbon, such that said surface of saidsemiconductor substrate is exposed, and said step of etching causesformation of a layer injected with carbon in said exposed surface ofsaid semiconductor substrate; and exposing said layer to plasmacontaining oxygen radicals and two or more radicals other than oxygen.2. The method as claimed in claim 1, wherein said surface of saidsemiconductor substrate contains Si atoms and wherein said damaged layercontains SiC.
 3. The method as claimed in claim 1, wherein saidsemiconductor substrate comprises a silicon substrate.
 4. The method asclaimed in claim 1, wherein said step of etching further exposes apolysilicon surface of said gate electrode.
 5. The method as claimed inclaim 1, wherein said gate electrode has a gate length of 90 nm or less.6. The method as claimed in claim 1, further comprising a step ofetching said layer exposed to said plasma by a wet etching process. 7.The method as claimed in claim 6, further comprising, after said wetetching process, introducing an impurity element into said semiconductorsubstrate by an ion implantation process.
 8. The method as claimed inclaim 7, further comprising a step of forming a silicide layer on saidsemiconductor substrate.
 9. The method as claimed in claim 6, whereinsaid wet etching process is conducted such that there are formed steppedparts at respective lateral sides of said sidewall insulation films. 10.The method as claimed in claim 9, wherein said wet etching process isconducted such that said stepped parts have a step height of 5 nm orless.
 11. The method as claimed in claim 9, wherein said wet etchingprocess is conducted such that said stepped parts have a step height of3 nm or less.
 12. The method as claimed in claim 1, wherein said gascontaining fluorocarbon contains carbon, fluorine and hydrogen.
 13. Themethod as claimed in claim 1, wherein said two or more radicals otherthan oxygen are selected from the group consisting of nitrogen, hydrogenand halogen.
 14. The method as claimed in claim 13, wherein said halogenis fluorine.
 15. A method of fabricating a semiconductor device,comprising the steps of: depositing a film over a surface of asemiconductor substrate; etching said film to form a contact hole byusing a gas containing fluorocarbon such that said contact hole exposessaid surface of said semiconductor substrate, and said step of etchingcauses formation of a layer injected with carbon; and exposing saidlayer to plasma containing oxygen radicals and two or more radicalsother than oxygen.